1. Field
Example embodiments relate to flash memory devices (e.g., flash memory devices and methods capable of improving the reliability of a reading operation).
2. Description of Conventional Art
Flash memory (e.g. NAND flash memory and NOR flash memory) is electronically erasable and writeable. Thus, flash memory devices may be used as system programming tools or subsidiary storage units.
NAND flash memory includes a memory cell array which functions as an information reservoir. The memory cells may be arranged at intersections of word lines and bit lines. Such an arrangement organizes the memory cell array into a plurality of cell strings (e.g. NAND strings). Also, NAND flash memory may include a page buffer circuit to store or read data from the memory cell array. A memory cell in NAND flash memory may be erased or programmed using Fowler-Nordheim (F-N) tunneling current.
During operation of a flash memory device, a reading operation is carried out in the flash memory to find out whether a particular memory cell is programmed or erased. During the reading operation, a word line is selected and a bit line is precharged to a specific voltage level. The precharging voltage level depends on the condition of the memory cell, which is coupled to the selected word line for a desired time (or, alternatively, a predetermined time). The bit line goes to a low level (e.g., the ground voltage level) if the memory cell coupled to the selected word line has been erased (i.e., on-cell), or maintains the precharging voltage level if the memory cell has been programmed (i.e., off-cell).
As the number of programming/erasing cycles increases, the programming characteristics of the memory cells may degrade. Memory cell degradation reduces the amount of current flowing through the memory cells. The memory cell with the worst programming characteristics is called a ‘worst on-cell’. If a selected memory cell is the worst on-cell, current flowing through the selected memory cell is at its lowest point.
Generally, turned-on memory cells have their own resistance values in correspondence with their channel widths. Furthermore, the resistance values of the turned-on memory cells are inversely proportional to gate-source potential gaps. During a reading operation, memory cells coupled to a non-selected word line are turned on. As a consequence, turning on the memory cells coupled to non-selected word lines causes the memory cells to have resistance. The resistance impacts the current flowing though the cell string, which connects the memory cell of a selected word line to deselected memory cells. The cell string connecting the non-selected memory cells to the selected memory cell causes the deselected memory cells to act as resistors connected in series.
A memory cell may be a memory cell transistor in which the current flowing through the memory cell transistor is proportional to the gate-source potential gap. If the non-selected memory cells are coupled to a source contact of a selected memory cell transistor, the source resistance may affect the current and voltage applied to the selected memory cell transistor. The source resistance is the combined resistance value caused by all the non-selected memory cells in a cell string connected to the source channel of a selected memory cell. A rise in the source resistance value leads the source voltage of the memory cell transistor to rise, which reduces the gate-source potential gap of the memory cell transistor. Since the current flowing through a turned-on memory cell is proportional to the gate-source potential gap, an increase in the source resistance value results in a reduction in the amount of current flowing through the selected memory cell transistor. The decrease in current flow is amplified with each additional deselected memory cell. Also, if the selected memory cell transistor is simultaneously the worst on-cell, the precharging voltage level of a bit line will not be able to discharge at a predetermined time, degrading the reliability of the operation.